High-Speed Binary Division
نویسندگان
چکیده
An augmented iterative array for binary division (IAD), is described. It uses carry-save reduction and carry-lookahead principles to achieve high speed. Logic cost and speed comparisons with two other design techniques are presented. An 8-bit prototype model that operates in under 500 ns has been built from commercially available high-speed MSI TTL integrated circuits to verify the feasibility of the IAD scheme.
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